1. Field of the Invention
The invention relates in general to a PCI bus compatible structure, and more particularly, to a PCI bus structure that supports multiple transmission speeds.
2. Description of the Related Art
FIG. 1 shows a structure using a PCI system in a normal computer. The central processing unit (CPU) 10 is coupled to the PCI bus 14 via the host bridge 12. The PCI bus 14 can be coupled to multiple masters 16a, 16b, 16c and 16d of PCI compatible peripherals. Each master can send a request signal (REQ) to require using the PCI bus 14. The arbiter in the host bridge 12 then sends the grant signal (GNT) to the master to grant the usage of the PCI bus 14.
The data transmission between the PCI compatible peripherals (such as the masters or the north bridge of the computer chip set) is controlled by the following interface control signals. The cycle frame signal FRAME# is asserted by an initiator (such as the masters or the north bridge) to confirm whether the transmission data is the last batch of data. When the cycle frame signal FRAME# is output, it indicates that the transaction of the data transmission via the PCI bus is started. As long as the cycle frame signal FRAME# remains in a low potential, the transaction of the data transmission continues. Meanwhile, the AD (data address signal) bus outputs a valid address during the address cycle and outputs a valid bus command during command/byte enable (CBE[3:0]) to indicate the data transaction type required by the initiator to a target. Right after all the valid addresses are output, the AD bus outputs the data to be transmitted, which is called the data cycle. Meanwhile, the byte enable signal of bus command after coding is output from the CBE line to transmit data. Cessation of output of the cycle frame signal FRAME# means the transaction status is transmitting the last batch of data, or the data transmission is complete. The initiator ready signal IRDY# and the target ready signal TRDY# are used to respectively indicate that the initiator and the target are ready to perform data transmission. In a read operation, the IRDY# signal means that the initiator is ready to receive data. When entering a write operation, the TRDY# signal indicates that the target is ready to receive data. The stop signal STOP# is used to indicate the target to request the initiator stopping the current transaction of data transmission.
However, during transmission, all the signals are transmitted according to the 33 MHz bus clock, and are triggered according to the rising edge of the clock. Thus, the data signal in one clock cycle can only transmit a set of data. Therefore, the data transmission speed is restricted by the bus clock and cannot cope with the requirements of high speed of data transmission.